1. Field of the Invention
This invention is related to integrated circuits, and more particularly, to the testing of integrated circuits having I/O pins that support plesiochronous interconnect.
2. Description of the Related Art
Plesiochronous signaling is a form of high-speed signaling capable of enabling chip-to-chip communications having transfer rates of up to 10 Gbits/s over a single interconnection. As such, plesiochronous links are capable of significantly higher data transfer speeds than traditional synchronous links (synchronized to a global clock) or source synchronous links (synchronized by a clock transmitted concurrently with the data). Instead of relying on a separate clock signal, plesiochronous links utilize an embedded clock signal, which is recovered from transmitted data by a clock-and-data recovery (CDR) circuit.
Due to the obvious speed advantages of plesiochronous links, many systems now utilize integrated circuits (IC's) configured to communicate with each other in this manner. However, configuring the I/O pins of an integrated circuit package for plesiochronous communications may present a significant obstacle to performing manufacturing tests thereupon.
Manufacturing tests of integrated circuits on automated test equipment (ATE) requires the ATE to be able to drive chip stimulus on input pins with reference to a clock so that the test stimulus is deterministic in time with respect to the ATE. These test stimuli are generated by an ATE program and received by the chip under test to perform test functions on the logic inside the chip. However, receiver pins and circuitry configured for plesiochronous reception of signals do not satisfy the ATE requirement of relying on a reference clock to align the test stimulus. Furthermore, a typical ATE system is not capable of generating test stimulus with the plesiochronous protocol information for alignment embedded within. Even if an ATE system could generate such a test stimulus stream, there is still a problem of misalignment with the test response to this stimulus, which will be misaligned with reference to the ATE internal clock on which the stimulus is sent.
To work around this limitation, IC's configured to receive data plesiochronously may include dedicated test pins that can synchronously receive test vectors or other stimulus from ATE. However, this solution is expensive, as it consumes silicon area on the die and pin count on the IC package. Furthermore, the number of dedicated test pins may be limited by other specifications of the IC. Limiting the number of dedicated test pins may in turn reduce the communications bandwidth between the IC and the ATE, increase the amount of time necessary to test the IC, or cause a reduction in the amount of testing that can be performed. Thus, for IC's configured to receive signals plesiochronously, testing may be significantly constrained.